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<div id="catalog">
<ul>
<li><a href="#Message" style=" font-size: 16px;">Pin Messages</a></li>
<!--<li><a href="#Summary" style=" font-size: 16px;">Pin Summaries</a></li>-->
<li><a href="#Pin_Details" style=" font-size: 16px;">Pin Details</a>
<ul>
<li><a href="#Pinout_by_Port_Name" style=" font-size: 14px;">Pinout by Port Name</a></li>
<li><a href="#All_Package_Pins" style=" font-size: 14px;">All Package Pins</a></li>
</ul>
</li>
</ul>
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<div id="content">
<h1><a name="Message">Pin Messages</a></h1>
<table class="summary_table">
<tr>
<td class="label">Report Title</td>
<td>Pin Report</td>
</tr>
<tr>
<td class="label">Design File</td>
<td>C:\Users\yami\Documents\RVX32\impl\gwsynthesis\RVX32.vg</td>
</tr>
<tr>
<td class="label">Physical Constraints File</td>
<td>C:\Users\yami\Documents\RVX32\src\RVX32.cst</td>
</tr>
<tr>
<td class="label">Timing Constraints File</td>
<td>---</td>
</tr>
<tr>
<td class="label">Version</td>
<td>V1.9.8.07</td>
</tr>
<tr>
<td class="label">Part Number</td>
<td>GW1NZ-LV1QN48C6/I5</td>
</tr>
<tr>
<td class="label">Device</td>
<td>GW1NZ-1</td>
</tr>
<tr>
<td class="label">Created Time</td>
<td>Tue Nov 29 14:47:26 2022
</td>
</tr>
<tr>
<td class="label">Legal Announcement</td>
<td>Copyright (C)2014-2022 Gowin Semiconductor Corporation. All rights reserved.</td>
</tr>
</table>
<h1><a name="Pin_Details">Pin Details</a></h1>
<h2><a name="Pinout_by_Port_Name">Pinout by Port Name:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Port Name</b></td>
<td><b>Diff Pair</b></td>
<td><b>Loc./Bank</b></td>
<td><b>Constraint</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Slew Rate</b></td>
<td><b>BankVccio</b></td>
</tr>
<tr>
<td class="label">data_in</td>
<td></td>
<td>31/1</td>
<td>Y</td>
<td>in</td>
<td>IOR6[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">data_cs</td>
<td></td>
<td>20/1</td>
<td>Y</td>
<td>in</td>
<td>IOR10[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>DOWN</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">data_dir</td>
<td></td>
<td>19/1</td>
<td>Y</td>
<td>in</td>
<td>IOR6[J]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">clk</td>
<td></td>
<td>29/1</td>
<td>Y</td>
<td>in</td>
<td>IOR6[E]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">cpu_run</td>
<td></td>
<td>34/1</td>
<td>Y</td>
<td>in</td>
<td>IOR3[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>DOWN</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">sys_clk</td>
<td></td>
<td>47/0</td>
<td>Y</td>
<td>in</td>
<td>IOT10[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">data_out</td>
<td></td>
<td>30/1</td>
<td>Y</td>
<td>out</td>
<td>IOR6[C]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">led[0]</td>
<td></td>
<td>9/1</td>
<td>Y</td>
<td>out</td>
<td>IOR2[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">led[1]</td>
<td></td>
<td>11/1</td>
<td>Y</td>
<td>out</td>
<td>IOR3[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">led[2]</td>
<td></td>
<td>10/1</td>
<td>Y</td>
<td>out</td>
<td>IOR2[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">xdata</td>
<td></td>
<td>35/0</td>
<td>Y</td>
<td>out</td>
<td>IOT17[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>1.8</td>
</tr>
</table>
<br/>
<h2><a name="All_Package_Pins">All Package Pins:</a></h2>
<table class="summary_table">
<tr>
<td class="label"><b>Loc./Bank</b></td>
<td><b>Signal</b></td>
<td><b>Dir.</b></td>
<td><b>Site</b></td>
<td><b>IO Type</b></td>
<td><b>Drive</b></td>
<td><b>Pull Mode</b></td>
<td><b>PCI Clamp</b></td>
<td><b>Hysteresis</b></td>
<td><b>Open Drain</b></td>
<td><b>Slew Rate</b></td>
<td><b>Bank Vccio</b></td>
</tr>
<tr>
<td class="label">4/0</td>
<td>-</td>
<td>in</td>
<td>IOT7[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">3/0</td>
<td>-</td>
<td>in</td>
<td>IOT7[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">5/0</td>
<td>-</td>
<td>in</td>
<td>IOT8[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">7/0</td>
<td>-</td>
<td>out</td>
<td>IOT8[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">6/0</td>
<td>-</td>
<td>in</td>
<td>IOT9[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">48/0</td>
<td>-</td>
<td>in</td>
<td>IOT9[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">47/0</td>
<td>sys_clk</td>
<td>in</td>
<td>IOT10[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">8/0</td>
<td>-</td>
<td>in</td>
<td>IOT10[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">46/0</td>
<td>-</td>
<td>in</td>
<td>IOT12[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">45/0</td>
<td>-</td>
<td>in</td>
<td>IOT12[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">44/0</td>
<td>-</td>
<td>in</td>
<td>IOT13[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">43/0</td>
<td>-</td>
<td>in</td>
<td>IOT14[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">42/0</td>
<td>-</td>
<td>in</td>
<td>IOT14[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">41/0</td>
<td>-</td>
<td>in</td>
<td>IOT15[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">40/0</td>
<td>-</td>
<td>in</td>
<td>IOT16[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">39/0</td>
<td>-</td>
<td>in</td>
<td>IOT16[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">38/0</td>
<td>-</td>
<td>in</td>
<td>IOT17[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">35/0</td>
<td>xdata</td>
<td>out</td>
<td>IOT17[B]</td>
<td>LVCMOS18</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>1.8</td>
</tr>
<tr>
<td class="label">9/1</td>
<td>led[0]</td>
<td>out</td>
<td>IOR2[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">10/1</td>
<td>led[2]</td>
<td>out</td>
<td>IOR2[B]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">11/1</td>
<td>led[1]</td>
<td>out</td>
<td>IOR3[A]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">34/1</td>
<td>cpu_run</td>
<td>in</td>
<td>IOR3[B]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>DOWN</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">33/1</td>
<td>-</td>
<td>in</td>
<td>IOR5[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">32/1</td>
<td>-</td>
<td>in</td>
<td>IOR5[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">31/1</td>
<td>data_in</td>
<td>in</td>
<td>IOR6[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">14/1</td>
<td>-</td>
<td>in</td>
<td>IOR6[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">30/1</td>
<td>data_out</td>
<td>out</td>
<td>IOR6[C]</td>
<td>LVCMOS33</td>
<td>8</td>
<td>UP</td>
<td>NA</td>
<td>NA</td>
<td>OFF</td>
<td>FAST</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">15/1</td>
<td>-</td>
<td>in</td>
<td>IOR6[D]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">29/1</td>
<td>clk</td>
<td>in</td>
<td>IOR6[E]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">16/1</td>
<td>-</td>
<td>in</td>
<td>IOR6[F]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">17/1</td>
<td>-</td>
<td>in</td>
<td>IOR6[G]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">18/1</td>
<td>-</td>
<td>in</td>
<td>IOR6[H]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">28/1</td>
<td>-</td>
<td>in</td>
<td>IOR6[I]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">19/1</td>
<td>data_dir</td>
<td>in</td>
<td>IOR6[J]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">27/1</td>
<td>-</td>
<td>in</td>
<td>IOR7[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">21/1</td>
<td>-</td>
<td>in</td>
<td>IOR7[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">24/1</td>
<td>-</td>
<td>in</td>
<td>IOR8[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">23/1</td>
<td>-</td>
<td>in</td>
<td>IOR8[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">22/1</td>
<td>-</td>
<td>in</td>
<td>IOR9[A]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">20/1</td>
<td>data_cs</td>
<td>in</td>
<td>IOR10[A]</td>
<td>LVCMOS33</td>
<td>NA</td>
<td>DOWN</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
<tr>
<td class="label">13/1</td>
<td>-</td>
<td>in</td>
<td>IOR10[B]</td>
<td>LVCMOS18</td>
<td>NA</td>
<td>UP</td>
<td>NA</td>
<td>NONE</td>
<td>NA</td>
<td>NA</td>
<td>3.3</td>
</tr>
</table>
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